Many electronic products need various amounts of memory to store information, e.g. data. One common type of high speed, low cost memory includes dynamic random access memory (DRAM) comprised of individual DRAM cells arranged in arrays. DRAM cells include an access transistor, e.g a metal oxide semiconducting field effect transistor (MOSFET), coupled to a capacitor cell.
Another type of high speed, low cost memory includes floating gate memory cells. A conventional horizontal floating gate transistor structure includes a source region and a drain region separated by a channel region in a horizontal substrate. A floating gate is separated by a thin tunnel gate oxide. The structure is programmed by storing a charge on the floating gate. A control gate is separated from the floating gate by an intergate dielectric. A charge stored on the floating gate effects the conductivity of the cell when a read voltage potential is applied to the control gate. The state of cell can thus be determined by sensing a change in the device conductivity between the programmed and un-programmed states.
With successive generations of DRAM chips, an emphasis continues to be placed on increasing array density and maximizing chip real estate while minimizing the cost of manufacture. It is further desirable to increase array density with little or no modification of the DRAM optimized process flow.
Multilayer insulators have been previously employed in memory devices. (See generally, U.S. Pat. No. 3,877,054, Boulin et al., Apr. 8, 1975, entitled “Semiconductor memory apparatus with a multi-layer insulator contacting the semiconductor,” and U.S. Pat. No. 3,964,085, Kahng et al., Jun. 15, 1976, entitled “Method for fabricating multilayer insulator-semiconductor memory apparatus”). The devices in the above references employed oxide-tungsten oxide-oxide layers. Other previously described structures described have employed charge-trapping layers implanted into graded layer insulator structures. (See generally, an article by DiMaria, D. J., “Graded or stepped energy band-gap-insulator MIS structures (GI-MIS or SI-MIS),” Journal of Applied Physics, 50(9), 5826-9 (September 1979); U.S. Pat. No. 4,217,601, DeKeersmaecker et al., Aug. 12, 1980, entitled “Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure,” also U.S. Pat. No. RE31,083 DeKeersmaecker et al., Nov. 16, 1982, “Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure;” and U.S. Pat. No. 5,768,192 Eitan, Jun. 16, 1998, entitled “Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping”).
More recently oxide-nitride-oxide structures have been described for high density nonvolatile memories. (See generally, Etian, B. et al., “NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., 21(11), 543-545 (November 2000), and Eitan, B. et al., “Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device, IEEE Electron Device Lett., 22(11), 556-558 (November 2001)). All of these are variations on the original MNOS memory structure (see generally, Frohman-Bentchkowsky, D., “An integrated metal-nitride-oxide-silicon (MNOS) memory,” Proceedings of the IEEE, 57(6), 1190-2 (June 1969)) described by Fairchild Semiconductor in 1969 which was conceptually generalized to include trapping insulators in general for constructing memory arrays. (See generally, U.S. Pat. No. 3,665,423 Nakamuma et al., May 23, 1972, entitled “Memory matrix using MIS semiconductor element”).
Studies of charge trapping in MNOS structures have also been conducted by White and others. (See generally, White, M. H., “Direct tunneling in metal-nitride-oxide-silicon (MNOS) structures,” Conference: Program of the 31st physical electronics conference (abstracts), page: 1 pp., Publisher: U.S. Dept. Commerce, Washington, D.C., USA, 1971, viii+46 Pages, Sponsor: American Phys. Soc., division of electron and atomic phys, 15-17 Mar. 1971, Gaithersburg, Md., USA; White, M. H., Cricchi, J. R., “Characterization of thin-oxide MNOS memory transistors,” IEEE Transactions on Electron Devices, ED-19(12), 1280-8 (December 1972), Wei, L. S., Simmons, J. G. “Trapping, emission and generation in MNOS memory devices,” Solid-State Electronics, 17(6), 591-8 (June 1974), Ferris-Prabhu, A. V., “Charge transfer in layered insulators,” Solid-State Electronics, 16(9), 1086-7 (September 1973); Ferris-Prabhu, A. V., Lareau, L. J., “Amnesia in layered insulator FET memory devices,” Conference: 1973 International Electron Devices Meeting Technical Digest, Page: 75-7, Publisher: IEEE, New York, N.Y., USA, 1973, xvi+575 Pages, Sponsor: IEEE, 3-5 Dec. 1973, Washington, D.C., USA; Ferris-Prabhu, A. V., “Tunneling theories of non-volatile semiconductor memories,” Physica Status Solidi A, 35(1), 243-50 (16 May 1976)).
Some commercial and military applications utilized non-volatile MNOS memories. (See generally, Britton, J. et al., “Metal-nitride-oxide IC memory retains data for meter reader,” Electronics, 45(22); 119-23 (23 Oct. 1972); and Cricchi, J. R. et al., “Hardened MNOS/SOS electrically reprogrammable nonvolatile memory,” IEEE Transactions on Nuclear Science, ns-24(6), 2185-9 (December 1977), Conference: IEEE Annual Conference on Nuclear and Space Radiation Effects, Sponsor: IEEE, 12-15 Jul. 1977, Williamsburg, Va., USA).
However, these structures did not gain widespread acceptance and use due to their variability in characteristics and unpredictable charge trapping phenomena. They all depended upon the trapping of charge at interface states between the oxide and other insulator layers or poorly characterized charge trapping centers in the insulator layers themselves. Since the layers were deposited by CVD, they are thick, have poorly controlled thickness and large surface state charge-trapping center densities between the layers.
Thus, there is an ongoing need for improved DRAM technology compatible transistor cells. It is desirable that such transistor cells be fabricated on a DRAM chip with little or no modification of the DRAM process flow. It is further desirable that such transistor cells provide increased density and high access and read speeds.